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? semiconductor MSM548512L 1/12 ? semiconductor MSM548512L 524,288-word 8-bit high-speed psram description the MSM548512L is fabricated using okis cmos silicon gate process technology. this process, coupled with single-transister memory storage cells, permits maximum circuit density, minimum chip size and high speed. MSM548512L has self-refresh mode in addition to address-refresh mode and auto-refresh mode. in the self-refresh mode the internal refresh timer and address counter refresh the dynamic memory cells automatically. this series allows low power consumption when using standby mode with self-refresh. the MSM548512L also features a static ram-like write function that writes the data into the memory cell at the rising edge of we . features ? large capacity : 4-mbit (524,288-word 8 bits) ? fast access time : 80 ns max. ? low power : 200 m a max. (standby with self-refresh) ? refresh free : self refresh ? logic compatible : sram we pin, no address multiplex ? single power supply : 5 v 10% ? refresh : 2048 cycle/32 ms auto-address refresh ? package compatible : sram standard package ? package options: 32-pin 600 mil plastic dip (dip32-p-600-2.54) (product : MSM548512L-xxrs) 32-pin 525 mil plastic sop (sop32-p-525-1.27-k) (product : MSM548512L-xxgs-k) xx indicates speed rank. product family family package access time (max.) MSM548512L-80rs MSM548512L-10rs MSM548512L-12rs 600 mil 32-pin plastic dip 80 ns 100 ns 120 ns MSM548512L-80gs-k MSM548512L-10gs-k MSM548512L-12gs-k 525 mil 32-pin plastic sop 80 ns 100 ns 120 ns this version: jan. 1998 previous version: dec. 1996 e2l0044-17-y1
? semiconductor MSM548512L 2/12 pin name function a 0 - a 18 v ss v cc we oe / rfsh ce i/o 0 - i/o 7 address input data input/output chip enable input output enable / refresh input write enable input power voltage (5 v) ground (0 v) pin configuration (top view) i/o 1 a 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss v cc a 15 a 17 we a 13 a 8 a 9 a 11 oe / rfsh a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin plastic dip 32-pin plastic sop a 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 2 v ss v cc a 15 a 17 we a 13 a 8 a 9 a 11 oe / rfsh a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3
? semiconductor MSM548512L 3/12 block diagram a 0 a 10 address latch control row decoder memory matrix (2048 256) 8 i/o 0 i/o 7 input data control column i/o column decoder address latch control a 11 a 18 timing pulse generator read/write control refresh control ce oe / rfsh we
? semiconductor MSM548512L 4/12 function table ce we mode l l i/o pin l h h oe / rfsh l x h l h h l h x x low-z high-z high-z high-z high-z read write refresh standby l : low level input h : high level input x : dont care absolute maximum ratings electrical characteristics voltage on any pin from v ss *1 parameter symbol unit power dissipation rating operating temperature storage temperature storage temperature (biased) short circuit output current v t p d t opr t stg t bias i os C1.0 to 7.0 1.0 0 to 70 C55 to 125 C10 to 85 50 v w c c c ma recommended operating conditions parameter power supply voltage symbol unit v cc max. typ. min. input voltage v ss v ih v il 4.5 0 2.4 C0.5 5.0 0 5.5 0 6.0 0.8 v v v v (ta = 0c to 70c) *1 to v ss note: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
? semiconductor MSM548512L 5/12 dc characteristics i sb1 parameter operating current symbol unit ma i cc1 ma min. standby current i cc2 m a i sb2 ma self refresh current i li m a i cc3 m a C10 input leakage current v ol output leakage current m a i lo C10 v output low level v oh v 2.4 output high level 50 1 typ. 100 1 100 75 2 max. 200 2 200 10 10 0.4 condition i i/o = open, t cyc = min. ce = v ih , oe / rfsh = v ih , v cc = 5.5 v, v in = v ss to v cc oe / rfsh = v ih , v i/o = v ss to v cc i ol = 2.1 ma i oh = C1 ma ce 3 v cc C 0.2 v, v in 3 0 v, ce = v ih , oe / rfsh = v il , ce 3 v cc C 0.2 v, v in 3 0 v, (v cc = 5 v 10%, v ss = 0 v, ta = 0c to 70c) v in 3 0 v oe / rfsh 3 v cc C 0.2 v v in 3 0 v oe / rfsh 0.2 v capacitance note: this parameter is periodically sampled and is not 100% tested. c i/o parameter input capacitance symbol unit pf c in pf min. i/o pin capacitance typ. 8 10 max. condition v in = 0 v v i/o = 0 v
? semiconductor MSM548512L 6/12 ac characteristics measurement condition: input pulse level ........................... v ih = 2.4 v, v il = 0.4 v output reference level .................. v oh = 2.0 v, v ol = 0.8 v rising and falling time ................. 5 ns output load .................................... 1 ttl + 100 pf input timing reference level ........ high = 2.2 v, low = 0.8 v parameter symbol MSM548512L -12 note t rc random read write cycle time 210 max. min. unit ns MSM548512L -10 180 max. min. MSM548512L -80 160 max. min. t rwc random read modify write cycle time 280 ns 240 220 t cea ce access time 120 ns 100 80 t oea oe access time 50ns 30 30 t chz chip disable to output in high-z 6 30ns 30 25 t clz ce to output in low-z 20 ns 20 20 t ohz oe disable to output in high-z 6 30ns 25 25 t olz oe output in low-z 0ns 0 0 t ce ce pulse width 120n 10 m s 100n 10 m 80n 10 m t p ce precharge time 80 ns 70 70 t as address set-up time 0ns 0 0 t ah address hold time 30 ns 25 20 t rcs read command set-up time 0ns 0 0 t rch read command hold time 0ns 0 0 t wp write command pulse width 35 ns 30 25 t cw chip enable time 120 ns 100 80 t dw input data set time 30 ns 25 20 t dh input data hold time 0ns 0 0 t ow output active from end of write 5ns 5 5 t whz write enable to output in high-z 6 30ns 25 20 t t transition time 11 350ns 350 350 t rfd rfsh delay time from ce 80 ns 70 70 t fp rfsh precharge time 40 ns 40 40 t fap rfsh pulse width (auto-refresh) 80n 8 m s 80n 8 m 80n 8 m t fc auto-refresh cycle time 210 ns 180 160 t ohc oe command hold time 15 ns 15 15 t ocd oe delay time 0ns 0 0 t fas 8 m s 8 8 t rfs ce delay time from rfsh in self-refresh mode 600 ns 600 600 t ref refresh period (2048 cycle/32 ms) 32ms 32 32 (v cc = 5 v 10%, ta = 0c to 70c) rfsh pulse width (self-refresh)
? semiconductor MSM548512L 7/12 notes: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to ground. 3. i cc1 depends on output loading. specified values are obtained with the output open. 4. an initial pause of 100 m s is required after power-up followed by more than 8 initial cycles before proper device operation is achieved. 5. ac measurements assume t t = 5 ns. 6. t chz , t whz and t ohz define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. in write cycles, the input data is latched at the earlier rising point of either ce or we . write operation is achieved when both ce and we are low. 8. the i/o state remains at high impedance after ce goes low if the transition occurs at the same time as or after the falling edge of we . 9. use we or oe or both signals to disable the output before input data is applied during a write cycle when the input is not the same. 10. data input must be set to floating state before i/o becomes low impedance by we or oe or both. 11. v ih (min.) and v il (max.) are input timing reference levels for measurement. the transition time is measured between v il and v ih . 12. 2048-cycle refresh must be applied within 15 m s after the end of self refreshing to satisfy 2048 cycles/32 ms.
? semiconductor MSM548512L 8/12 timing waveform read cycle write cycle 1 ( oe high) address a0 - a18 ce we oe / rfsh d out t rc t ce t p t as t ah "h" or "l" d in t cw t wp t dw t dh t whz t ohz t clz t ow t olz t chz valid data-in t ocd valid data-out address a0 - a18 ce we oe / rsfh d out t rc t ce t p t as t ah t rcs t cea t rch t oea t olz t chz t ohz "h" or "l" t ohc
? semiconductor MSM548512L 9/12 write cycle 2 ( oe low) address a0 - a18 ce we oe / rfsh d out t rc t ce t p t as t ah "h" or "l" d in t dw t dh t whz t clz valid data-in t wp t cw t ohc read modify write address a0 - a18 ce we oe / rfsh d out t as t ah "h" or "l" d in valid data-in t rwc t p t rcs t wp t rch t ohz t oea t dw t dh t olz t clz t whz t ow t chz valid data-out t cw t ocd t ohc
? semiconductor MSM548512L 10/12 auto refresh cycle self refresh cycle ce oe / rfsh "h" or "l" t rfd t fc t fc t fap t fp t fap t fp ce oe / rfsh "h" or "l" t rfd t fp t fas t rfs
? semiconductor MSM548512L 11/12 (unit : mm) package dimensions dip32-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 4.70 typ.
? semiconductor MSM548512L 12/12 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.32 typ. sop32-p-525-1.27-k mirror finish

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